After reviewing thousands of PCB design files, our engineering team has seen the same mistakes appear repeatedly — from startup prototypes to production board revisions at established companies. Most of these errors are invisible in EDA tools and pass DRC cleanly, but they cause real failures on the manufacturing floor or in the field.
This is a field guide to the seven most impactful PCB design mistakes, with concrete rules you can apply today.
When two pads are close together, the solder mask opening between them can be too narrow to reliably print. A solder mask sliver narrower than 0.1 mm (4 mil) may peel off during solder reflow, causing bridging. The pad geometry looks correct in your EDA tool — the DRC passes — but the board comes back with shorts.
Adjacent IC pads with 0.05 mm solder mask sliver between them. Passes DRC but fails at fab. Common on 0.4 mm pitch QFPs with default mask expansion.
Reduce mask expansion so the sliver is ≥ 0.1 mm, or use solder mask defined (SMD) pads. Verify with your fab's minimum solder mask bridge specification.
Rule: always request your fab's minimum solder mask web dimension before finalizing pad geometry on fine-pitch components.
Copper too close to the board edge gets damaged during depaneling (routing or V-scoring). The standard minimum is 0.3 mm for routed boards and 0.5 mm for V-scored boards. Traces that violate this appear fine in Gerber viewers but get nicked by the routing bit, causing intermittent opens in the field — the worst kind of failure because it can be environmental (vibration-triggered).
For castellated boards (edge-mount PCBs), this constraint inverts — the copper must intentionally extend to the board edge. Specify castellated holes explicitly in your fab notes and confirm your fab's support for this feature.
Placing vias inside SMT pads (via-in-pad) is an excellent HDI technique for BGA breakout. The mistake is specifying it without requesting via fill. An unfilled via-in-pad creates a solder trap — molten solder flows into the via barrel instead of forming a proper joint with the component. The result is a weak or open solder joint, impossible to detect without X-ray.
If you use via-in-pad, always specify: filled and capped via (copper-filled and planarized flush with the pad surface). This is a specific fabrication step that adds cost — but the alternative is unreliable joints on your most critical component interfaces.
A controlled impedance callout on your fab drawing without a complete stackup specification is effectively meaningless. The fabricator needs to know the dielectric constant of each material, the layer thicknesses, and which layers are impedance-controlled — to calculate the trace widths that achieve your target.
Saying "50 Ω single-ended on layer 2" without specifying dielectric thickness and material puts the impedance calculation entirely in the hands of the fabricator — who may use a different material or thickness than your SI models assumed.
| What to specify | Why it matters |
|---|---|
| Dielectric material (e.g., FR4-TG170, Megtron 6) | Dk value directly determines trace width for target impedance |
| Core and prepreg thickness per layer | Dielectric thickness is the primary impedance variable |
| Target impedance ± tolerance (e.g., 50 Ω ±10%) | Tolerance determines whether fab needs test coupon |
| Which layer(s) are impedance-controlled | Fabricator only controls traces where specified |
| Test coupon required (yes/no) | TDR coupon provides traceability; often required for RF |
EDA tools apply thermal relief connections to all through-hole pads in copper pours by default. For signal pads, thermal relief is desirable — it prevents the pad from wicking heat into the plane during soldering. For high-current paths (power connectors, motor drivers, battery contacts), thermal relief is a mistake: it increases resistance and creates a current bottleneck at the pad connection.
Check every through-hole pad on high-current paths and override the thermal relief to a solid pour connection. Also ensure that the current-carrying trace width is adequate: as a practical rule, use at least 1 mm of trace width per amp for internal layers and 0.8 mm/A for external layers in free-air conditions. Use a dedicated calculator (Saturn PCB Toolkit, Polar SI9000) for anything above 3 A.
This is an assembly error that DRC will never catch. If your silkscreen doesn't clearly indicate polarity for diodes, tantalum capacitors, polarized electrolytic capacitors, and connectors, assemblers rely on the component datasheet and pick-and-place file rotation — and discrepancies happen.
Best practice: mark every polarized component with a visible "+" or "1" on the silkscreen, placed so it remains visible after the component is placed. Don't rely solely on the cathode band mark — screen it explicitly. On dense boards where silkscreen doesn't fit under the component, add the marker adjacent to the component boundary.
The most systemic mistake: treating the Gerber, BOM, and pick-and-place file as three independent documents and generating them at different stages of the design.
Fix Generate all output files from a single, locked design revision in the same EDA session. Tag the revision in your version control. Never patch Gerbers manually.
None of these mistakes are exotic edge cases — they appear in designs from experienced engineers every week. The common thread is that EDA tools are optimized for electrical correctness, not for manufacturing context. The manufacturing constraints live in your fabricator's process capability documents, not in your DRC ruleset.
The fastest way to close this gap is a DFM review before you release to fab. At DUXPCB, every order includes a complimentary engineering DFM review — we catch these issues before a single panel is run, so your first build is your best build.
Submit your design files for a free DFM review. Our engineers respond within 24 hours.
